1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and particularly to a process for etching an opening in semiconductor structures and more particularly to an etch method to form a contact hole in a dielectric film.
2) Description of the Prior Art
In the manufacture of integrated circuits, silicon-containing layers on a substrate are etched to form gates, vias, contact holes, trenches, and/or interconnect lines. The etched areas are later filled with electrically conductive material to form electrically conductive interconnects or with insulating materials in the case of gate structures. Examples of such silicon-containing materials include silicon dioxide, silicon nitride, polysilicon, metal silicide, and monocrystalline silicon. The substrate may also contain layers of other materials, for example metal conductor layers, insulative layers, anti-reflective layers, or diffusion layers, among others.
In a typical etching process, a patterned mask composed of a material less susceptive to etching, such as photoresist, or a hard mask layer such as silicon dioxide or silicon nitride, is formed over the substrate. Thereafter, the substrate is placed within a process chamber and etched by a plasma of etchant gas in the chamber. The residue of material deposited on the substrate is then etched. The composition of the residue is dependent upon the etchant gas that is used, the substrate material, and composition of the mask or resist layer.
The importance of overcoming the various deficiencies is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,505,816 (Barnes et al.) shows a process to etch oxide selectively to SiN and poly.
U.S. Pat. No. 6,583,065B1 (Williams) shows a sidewall polymer removing etch process.
U.S. Pat. No. 6,536,449B1 (Ranft et al.) shows a down stream plasma process.
Hu et al., “Resist stripping for multilevel interconnect integration with Low K dielectric material”, AVS first inter conference on Microelectronics and interface, February 2000.
U.S. Pat. No. 5,423,945 (Marks et al.) shows a selectivity for etching an oxide over a nitride.
There is a need for an improved etch process.